2 #include <FlashStorage.h>
16 const char *
function;
29 period = milliseconds;
43 Serial.print(
"Halted at ");
44 Serial.print(
function);
45 Serial.print(
", line ");
51 strncpy(buffer,
function, 100);
55 persistent.write(*
this);
60 *
this = persistent.read();
71 #if defined(ARDUINO_ARCH_SAMD)
73 void WDT_Handler(
void) {
74 WDT->INTFLAG.bit.EW = 1;
75 Serial.println(
"Watchdog!");
95 if(!_initialized) _initialize_wdt();
97 #if defined(__SAMD51__)
99 while(WDT->SYNCBUSY.reg);
102 while(WDT->STATUS.bit.SYNCBUSY);
105 if((maxPeriodMS >= 8000) || !maxPeriodMS) {
108 cycles = maxPeriodMS >> 2;
111 while( cycles = cycles>>1){
134 #if defined(__SAMD51__)
135 WDT->INTFLAG.bit.EW = 1;
136 WDT->INTENSET.bit.EW = 1;
137 WDT->CONFIG.bit.PER = bits+1;
138 WDT->EWCTRL.bit.EWOFFSET = bits;
139 WDT->CTRLA.bit.WEN = 0;
140 while(WDT->SYNCBUSY.reg);
142 WDT->CTRLA.bit.ENABLE = 1;
143 while(WDT->SYNCBUSY.reg);
145 WDT->INTENSET.bit.EW = 1;
146 WDT->CONFIG.bit.PER = bits+1;
147 WDT->EWCTRL.bit.EWOFFSET = bits;
148 WDT->CTRL.bit.WEN = 0;
149 while(WDT->STATUS.bit.SYNCBUSY);
151 WDT->CTRL.bit.ENABLE = 1;
152 while(WDT->STATUS.bit.SYNCBUSY);
161 #if defined(__SAMD51__)
162 while(WDT->SYNCBUSY.reg);
164 while(WDT->STATUS.bit.SYNCBUSY);
166 WDT->CLEAR.reg = WDT_CLEAR_CLEAR_KEY;
171 #if defined(__SAMD51__)
172 return RSTC->RCAUSE.reg;
174 return PM->RCAUSE.reg;
179 #if defined(__SAMD51__)
180 WDT->CTRLA.bit.ENABLE = 0;
181 while(WDT->SYNCBUSY.reg);
183 WDT->CTRL.bit.ENABLE = 0;
184 while(WDT->STATUS.bit.SYNCBUSY);
188 void WatchdogSAMD::_initialize_wdt() {
192 #if defined(__SAMD51__)
195 OSC32KCTRL->OSCULP32K.bit.EN1K = 1;
196 OSC32KCTRL->OSCULP32K.bit.EN32K = 0;
199 NVIC_DisableIRQ(WDT_IRQn);
200 NVIC_ClearPendingIRQ(WDT_IRQn);
201 NVIC_SetPriority(WDT_IRQn, 0);
202 NVIC_EnableIRQ(WDT_IRQn);
204 while(WDT->SYNCBUSY.reg);
206 USB->DEVICE.CTRLA.bit.ENABLE = 0;
207 while(USB->DEVICE.SYNCBUSY.bit.ENABLE);
208 USB->DEVICE.CTRLA.bit.RUNSTDBY = 0;
209 USB->DEVICE.CTRLA.bit.ENABLE = 1;
210 while(USB->DEVICE.SYNCBUSY.bit.ENABLE);
213 GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(4);
216 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) |
218 GCLK_GENCTRL_SRC_OSCULP32K |
220 while(GCLK->STATUS.bit.SYNCBUSY);
222 GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT |
224 GCLK_CLKCTRL_GEN_GCLK2;
227 NVIC_DisableIRQ(WDT_IRQn);
228 NVIC_ClearPendingIRQ(WDT_IRQn);
229 NVIC_SetPriority(WDT_IRQn, 0);
230 NVIC_EnableIRQ(WDT_IRQn);
236 #endif // defined(ARDUINO_ARCH_SAMD)